45nm Transistor Reliability

It has been clear for a number of years that increasing transistor gate leakage with device scaling would ultimately necessitate an alternative to traditional SiON dielectrics with polysilicon gates. Material systems providing higher dielectric constants, and therefore allowing physically thicker dielectrics, have been the object of extensive research. Such high-k dielectrics, when combined with metal gate electrodes, have emerged as the leading alternative, demonstrating good transistor performance and offering reductions in gate leakage of 25X-100X. Achieving the required reliability, particularly at the high operating electric fields at which the performance advantages are realized, however, proved much more difficult. Intel strove to overcome the reliability obstacles by introducing high-k dielectrics combined with metal gate electrodes (HK+MG) transistors in its 45nm logic process, as it judged the transition to this technology would provide compelling performance advantages. In this paper we discuss the general considerations for the reliability of HK+MG transistors and specifically we discuss what was achieved with Intel’s 45nm process technology. A particularly extensive effort was undertaken to characterize the reliability physics of this revolutionary new transistor and to gather the data to ensure accurate modeling of failure rates. This entailed accelerated testing and fully integrated test vehicles, representing over seven orders of magnitude in the transistor area, at a variety of stress conditions, some of which lasted over three months. The intrinsic transistor reliability fail modes addressed in this paper fall into two basic classes. First we have the integrity of the transistor dielectric itself, which in the course of operation, can fail, a phenomenon typically referred to as Time Dependent Dielectric Breakdown (TDDB). The transistor must be engineered to ensure that components don’t wear out within their operating lifetimes. Second, in addition to abrupt failure of the dielectric, transistors can also experience progressive parametric degradation. The primary parametric reliability mode for traditional SiON-based transistors is a slowdown of the PMOS devices due to progressive trapping of charge, typically referred to as Bias Temp Instability (BTI). For HK-based dielectrics, at their higher target operating fields, similar degradation is observed on NMOS transistors as well as potentially significant increases in gate leakage with stress, known as Stress Induced Leakage Current (SILC). We discuss these reliability phenomena and illustrate that while they pose large reliability challenges for HK+MG, these challenges can be overcome through refinement of process architecture and optimization of processing conditions. Intel’s 45nm technology is shown to achieve intrinsic TDDB and aggregate (N+P) BTI performance equivalent to its 65nm predecessor with negligible SILC at its 30% higher operating electric fields. PROCESS BACKGROUND The 45nm high-k dielectrics combined with metal gate electrodes (HK+MG) transistors studied in this work have a Hafnium-based gate dielectric and dual workfunction Intel Technology Journal, Volume 12, Issue 2, 2008 45nm Transistor Reliability 132 metal gate electrodes for NMOS and PMOS. The transistor fabrication utilizes a HK first and MG last process as detailed in [1]. In this flow, HK is deposited using an Atomic Layer Deposition (ALD) process, and polysilicon is used for the gate patterning. After the Interconnect Dielectric deposition, a polish step exposes poly gates, and the dummy poly is removed. Then, workfunction metal electrodes are deposited followed by a gate fill process. The SiO2 equivalent oxide thickness (EOT) of the HK plus the Interface Layer (IL) that forms between the HK and the silicon is ~1.0nm. Figure 1 describes the gate stack, with its SiO2-like interface layer (IL) and the HK dielectric proper.